document no. e0785e10 (ver. 1.0) date published august 2005 (k) japan printed in japan url: http://www.elpida.com ? elpida memory, inc. 2005 preliminary data sheet 512m bits ddr3 sdram edj5304aase (128m words 4 bits) edj5308aase (64m words 8 bits) edj5316aase (32m words 16 bits) description the edj5304aase is a 512m bits ddr3 sdram organized as 16,777,216 words 4 bits 8 banks. the edj5308aase is a 512m bits ddr3 sdram organized as 8,388,608 words 8 bits 8 banks. they are packaged in 78-ball fbga ( bga ? ) package. the edj5316aase is a 512m bits ddr3 sdram organized as 4,194,304 words 16 bits 8 banks. it is packaged in 96-ball fbga ( bga ? ) package. features ? power supply: vdd, vddq = 1.5v 0.075v ? data rate: 1333mbps/1066mbps (max.) ? double-data-rate architecture: two data transfers per clock cycle ? bi-directional, differential data strobe (dqs and /dqs) is transmitted/received with data, to be used in capturing data at the receiver ? dqs is edge aligned with data for reads: center- aligned with data for writes ? differential clock inputs (ck and /ck) ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge: data and data mask referenced to both edges of dqs ? 8 internal banks for concurrent operation ? data mask (dm) for write data ? burst lengths (bl): 4, 8 and 4 with burst chop ? /cas latency (cl): 5, 6, 7, 8, 9, 10 ? /cas write latency (cwl): 5, 6, 7, 8 ? auto precharge operation for each burst access ? auto refresh and self refresh modes ? average refresh period: 7.8 s ? 1.5v i/o ? posted cas by programmable additive latency for better command and data bus efficiency ? on-die-termination for better signal quality ? programmable partial array self refresh ? zq calibration for dq drive and on-die-termination ? reset-pin for power-up sequence and reset- function ? fbga ( bga) package with lead free solder (sn-ag-cu) ? rohs compliant
edj5304aase, edj5308aase, edj5316aase preliminary data sheet e0785e10 (ver. 1.0) 2 ordering information part number mask version organization (words bits) internal banks speed bin (cl-trcd-trp) package edj5304aase-dg-e edj5304aase-dj-e edj5304aase-ac-e edj5304aase-ae-e edj5304aase-ag-e a 128m 4 8 d3-1333 (8-8-8) d3-1333 (9-9-9) d3-1066 (6-6-6) d3-1066 (7-7-7) d3-1066 (8-8-8) 78-ball fbga ( bga) EDJ5308AASE-DG-E edj5308aase-dj-e edj5308aase-ac-e edj5308aase-ae-e edj5308aase-ag-e 64m 8 d3-1333 (8-8-8) d3-1333 (9-9-9) d3-1066 (6-6-6) d3-1066 (7-7-7) d3-1066 (8-8-8) edj5316aase-dg-e edj5316aase-dj-e edj5316aase-ac-e edj5316aase-ae-e edj5316aase-ag-e 32m 16 d3-1333 (8-8-8) d3-1333 (9-9-9) d3-1066 (6-6-6) d3-1066 (7-7-7) d3-1066 (8-8-8) 96-ball fbga ( bga) part number elpida memory density / bank 53: 512m / 8-bank organization 04: x4 08: x8 16: x16 power supply, interface a: 1.5v die rev. package se: fbga ( bga with back cover) speed dg: d3-1333 (8-8-8) dj: d3-1333 (9-9-9) ac: d3-1066 (6-6-6) ae: d3-1066 (7-7-7) ag: d3-1066 (8-8-8) product family j: ddr3 type d: monolithic device e d j 53 04 a a se - dg - e environment code e: lead free
edj5304aase, edj5308aase, edj5316aase preliminary data sheet e0785e10 (ver. 1.0) 3 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
edj5304aase, edj5308aase, edj5316aase preliminary data sheet e0785e10 (ver. 1.0) 4 bga is a registered trademark of tessera, inc. all other trademarks are the intellectual property of their respective owners. m01e0107 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] this product is not designed to be resistant to electromagnetic waves or radiation. this product must be used in a non-condensing environment. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.
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